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Publications and presentations

Books

1. K. Masu and S. Amakawa, Elementary Semiconductor Device Physics: Understanding Energy Band Formation Using Circuit Theory, CRC Press, 2024.
2. 益 一哉，天川修平，『電子物性とデバイス』（付録，正誤表） （書評），電子情報通信レクチャーシリーズA-9，コロナ社，2020．
3. M. Fujishima and S. Amakawa, Design of Terahertz CMOS Integrated Circuits for High-Speed Wireless Communication, IET, 2019.
4. 『ナノテクノロジーの化学』， 第5版実験化学講座第28巻，日本化学会編，丸善，2005（分担執筆）．
5. 『FreeBSD徹底入門 改訂版』，翔泳社，2002（分担執筆）．
6. 『SNMPネットワーク管理ツール』，翔泳社，2001（監訳）．
7. 『FreeBSD徹底活用１：ネットワーク編』，翔泳社，1998（分担執筆）．
8. 『FreeBSD徹底活用』，翔泳社，1997（分担執筆）．

Papers

• S. Tanaka, S. Hara, K. Takano, A. Kasamatsu, Y. Sugimoto, K. Sakakibara, S. Kubo, T. Yoshida, S. Amakawa, and M. Fujishima, "A 300-GHz-band 36-Gb/s scalable 2D phased-array CMOS double superheterodyne receiver," IEEE Solid-State Circuits Lett., vol. 8, pp. 133–136, 2025.
• D. Siebenkotten, B. Kästner, M. Marschall, A. Hoehl, and S. Amakawa, "Calibration method for complex permittivity measurements using s-SNOM combining multiple probe tapping harmonics," Opt. Express, vol. 32, no. 13, pp. 23882–23893, June 2024.
• S. Lee, S. Amakawa, T. Yoshida, and M. Fujishima, "A 58-%-lock-range divide-by-9 injection-locked frequency divider using harmonic-control technique," IEICE Trans. Electron., vol. E106-C, no. 10, pp. 529–532, October 2023.
• S. Lee, K. Takano, S. Amakawa, T. Yoshida, and M. Fujishima, "A 0.6-V 41.3-GHz power-scalable sub-sampling PLL in 55-nm CMOS DDC," IEICE Trans. Electron., vol. E106-C, no. 10, pp. 533–537, October 2023.
• S. Amakawa, R. Sugimoto, K. K. Tokgoz, S. Lee, H. Ito, and R. Kishikawa, "Signal-flow-graph analysis of weakly nonlinear microwave circuits around a large-signal operating point," IEEE Trans. Microwave Theory Tech., vol. 71, no. 9, pp. 3722–3733, September 2023.
• S. Hara, R. Dong, S. Lee, K. Takano, N. Toshida, A. Kasamatsu, K. Sakakibara, T. Yoshida, S. Amakawa, and M. Fujishima, "A 76-Gbit/s 265-GHz CMOS receiver with WR-3.4 waveguide interface," IEEE J. Solid-State Circuits, vol. 57, no. 10, pp. 2988–2998, October 2022.
• S. Lee, S. Amakawa, T. Yoshida, and M. Fujishima, "A 0.4-V 29-GHz-bandwidth power-scalable distributed amplifier in 55-nm CMOS DDC process," IEICE Trans. Electron., vol. E105-C, no. 10, pp. 561–564, October 2022.
• Y. Morishita, S. Lee, T. Teraoka, R. Dong, Y. Kashino, H. Asano, S. Hara, K. Takano, K. Katayama, T. Sakamoto, N. Shirakata, K. Takinami, K. Takahashi, A. Kasamatsu, T. Yoshida, S. Amakawa, and M. Fujishima, "300-GHz-band OFDM video transmission with CMOS TX/RX modules and 40 dBi Cassegrain antenna toward 6G," IEICE Trans. Electron., vol. E104-C, no. 10, pp. 576–586, October 2021 (pdf).
• K. Ohmori and S. Amakawa, "Variable-temperature noise characterization of N-MOSFETs using an in-situ broadband amplifier," IEEE J. Electron Devices Soc., vol. 9, pp. 1227–1236, September 2021.
• S. Lee, S. Amakawa, T. Yoshida, S. Hara, and M. Fujishima, "A 32-Gb/s CMOS receiver with analog carrier recovery and synchronous QPSK demodulation," IEEE Microwave Compon. Lett., vol. 31, no. 6, pp. 768–770, June 2021.
• K. Ohmori and S. Amakawa, "Direct white noise characterization of short-channel MOSFETs," IEEE Trans. Electron Devices, vol. 68, no. 4, pp. 1478–1482, April 2021.
• S. Lee, S. Hara, T. Yoshida, S. Amakawa, R. Dong, A. Kasamatsu, J. Sato, and M. Fujishima, "An 80-Gb/s 300-GHz-band single-chip CMOS transceiver," IEEE J. Solid-State Circuits, vol. 54, no. 12, pp. 3577–3588, December 2019.
• 藤島実，天川修平，高塚弘隆， 「テラヘルツ通信を実現する300GHz帯CMOS送信機モジュール」，電子情報通信学会論文誌C, vol. J102-C, no. 12, pp. 348–355, December 2019.
• 藤島実，天川修平，高塚弘隆， 「低電源電圧ミリ波CMOS回路」，電子情報通信学会論文誌C, vol. J101-C, no. 9, pp. 362–369, September 2018.
• S. Hara, K. Katayama, K. Takano, R. Dong, I. Watanabe, N. Sekine, A. Kasamatsu, T. Yoshida, S. Amakawa, and M. Fujishima, "32-Gbit/s CMOS receivers in 300-GHz band," IEICE Trans. Electron., vol. E101-C, no. 7, pp. 464–471, July 2018 (pdf).
• M. Fujishima and S. Amakawa, "Integrated-circuit approaches to THz communications: Challenges, advances, and future prospects," IEICE Trans. Fundamentals, vol. E100-A, no. 2, pp. 516–523, February 2017.
• K. Katayama, K. Takano, S. Amakawa, S. Hara, A. Kasamatsu, K. Mizuno, K. Takahashi, T. Yoshida, and M. Fujishima, "A 300 GHz CMOS transmitter with 32-QAM 17.5 Gb/s/ch capability over six channels," IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 3037–3048, December 2016.
• S. Amakawa, "Scattered reflections on scattering parameters–Demystifying complex-referenced S parameters–," IEICE Trans. Electron., vol. E99-C, no. 10, pp. 1100–1112, October 2016 [Correction] .
• S. Hara, K. Katayama, K. Takano, I. Watanabe, N. Sekine, A. Kasamatsu, T. Yoshida, S. Amakawa, and M. Fujishima, "Compact 141-GHz differential amplifier with 20-dB peak gain and 22-GHz 3-dB bandwidth," IEICE Trans. Electron., vol. E99-C, no. 10, pp. 1156–1163, October 2016.
• K. Takano, K. Katayama, S. Amakawa, T. Yoshida, and M. Fujishima, "Wireless digital data transmission from a 300 GHz CMOS transmitter," Electron. Lett., vol. 52, no. 15, pp. 1353–1355, July 2016.
• M. Fujishima, S. Amakawa, K. Takano, K. Katayama, and T. Yoshida, "Terahertz CMOS design for low-power and high-speed wireless communication," IEICE Trans. Electron., vol. E98-C, no. 12, pp. 1091–1104, December 2015.
• M. Fujishima and S. Amakawa, "Recent progress and prospects of terahertz CMOS," IEICE Electron. Express, vol. 12, no. 13, pp. 20152006-1–20152006-7, July 2015.
• 安達拓史，本良瑞樹，片山光亮，高野恭弥，天川修平，吉田毅，藤島実， 「共振型CMOSプッシュプッシュ2逓倍器の設計」，電子情報通信学会論文誌C, vol. J97-C, no. 12, pp. 484–491, December 2014.
• K. Katayama, M. Motoyoshi, K. Takano, C. Y. Li, S. Amakawa, and M. Fujishima, "E-band 65nm CMOS low-noise amplifier design using gain-boost technique," IEICE Trans. Electron., vol. E97-C, no. 6, pp. 476–485, June 2014.
• K. Takano, S. Amakawa, K. Katayama, M. Motoyoshi, and M. Fujishima, "Modeling of short-millimeter-wave CMOS transmission line with lossy dielectrics with specific absorption spectrum," IEICE Trans. Electron., vol. E96-C, no. 10, pp. 1311–1318, March 2013.
• S.-y. Lee, H. Ito, S. Amakawa, N. Ishihara, and K. Masu, "An inductorless cascaded phase-locked loop with pulse injection locking technique in 90 nm CMOS" Int. J. Microw. Sci. Technol., vol. 2013, article ID 584341, pp. 1–11, 2013.
• S.-y. Lee, H. Ito, S. Amakawa, S. Tanoi, N. Ishihara, and K. Masu, "1.2–17.6 GHz ring-oscillator-based phase-locked loop with injection locking in 65 nm complementary metal oxide semiconductor," Jpn. J. Appl. Phys., vol. 51, no. 2S, 02BE03, February 2012.
• K. Nakano, S. Amakawa, N. Ishihara, and K. Masu, "RF signal generator using time domain harmonic suppression technique in 90 nm CMOS," IEICE Electronics Express, vol. 9, no. 4, pp. 270–275, February 2012
• 栗田洋一郎，本橋紀和，松井聡，副島康志，天川修平，益一哉，川野連也， 「 三次元IC間に挿入された配線体の高周波伝送特性」，エレクトロニクス実装学会誌， vol. 14, no. 6, pp. 501–506, September 2011.
• A. Shirane, Y. Mizuochi, S. Amakawa, N. Ishihara, and K. Masu, "A study of digitally controllable radio frequency micro electro mechanical systems inductor," Jpn. J. Appl. Phys., vol. 50, no. 5S1, 05EE01, May 2011.
• S. Amakawa, A. Toda, K. Ohyama, N. Higashiguchi, D. Hori, Y. Shintaku, M. Miyake, and M. Miura-Mattausch, "Universal relationship between substrate current and history effect in silicon-on-insulator metal-oxide-semiconductor field-effect transistors," Jpn. J. Appl. Phys., vol. 50, no. 4S, 04DC12, April 2011.
• T. Saito, A. Tanaka, T. Hayashi, H. Kikuchihara, T. Kanamoto, H. Masuda, M. Miyake, S. Amakawa, H. J. Mattausch, and M. Miura-Mattausch, "Modeling of reduced surface field laterally diffused metal oxide semiconductor for accurate prediction of junction condition on device characteristics," Jpn. J. Appl. Phys., vol. 50, no. 4S, 04DP03, April 2011.
• S.-Y. Lee, S. Amakawa, N. Ishihara, and K. Masu, "2.4–10 GHz low-noise injection-locked ring voltage controlled oscillator in 90 nm complementary metal oxide semiconductor," Jpn. J. Appl. Phys., vol. 50, no. 4S, 04DE03, April 2011.
• (Invited) N. Ishihara, S. Amakawa, and K. Masu, "RF CMOS integrated circuit: history, current status and future prospects," IEICE Trans. Fundamentals, vol. E94-A, no. 2, pp. 556–567, February 2011.
• K. Masu, S. Amakawa, H. Ito, and N. Ishihara, "Interconnect design challenges in nano CMOS circuit," Key Engineering Materials, vol. 470, pp. 224–230, February 2011.
• 畠山英樹，上道雄介，天川修平，石原昇，益一哉， 「 ウェーハレベルパッケージ技術による高周波インダクタの開発と回路応用」， 電子情報通信学会論文誌C，vol. J93-C, no. 11, pp. 477–484, November 2010.
• T. Sekiguchi, S. Amakawa, N. Ishihara, and K. Masu, "Inductorless 8.9 mW 25 Gb/s 1:4 DEMUX and 4 mW 13 Gb/s 4:1 MUX in 90 nm CMOS," J. Semicond. Technol. Sci., vol. 10, no. 3, pp. 404–407, September 2010.
• M. M. Othman, S. Amakawa, N. Ishihara, and K. Masu, "Wide-band, high linear low noise amplifier design in 0.18 μm CMOS technology," IEICE Electronics Express, vol. 7, no. 11, pp. 759–764, June 2010.
• Y. Mizuochi, S. Amakawa, N. Ishihara, and K. Masu, "Radio frequency micro electro mechanical systems inductor configurations for achieving large inductance variations and high Q-factors," Jpn. J. Appl. Phys., vol. 49, no. 5S2, 05FG02, May 2010.
• S. Amakawa, N. Ishihara, and K. Masu, "A thru-only de-embedding method for on-wafer characterization of multiport networks," in V. Zhurbenko, editor, Advanced Microwave Circuits and Systems, pp. 13–32, INTECH, April 2010 [Errata].
• T. Oshita, S. Amakawa, N. Ishihara, and K. Masu, "Design of on-chip high speed interconnect on complementary metal oxide semiconductor 180 nm technology," Jpn. J. Appl. Phys., vol. 49, no. 4S, 04DE14, April 2010.
• K. Nakano, S. Amakawa, N. Ishihara, and K. Masu, "RF signal generator based on time-to-analog converter in 0.18 μm complementary metal oxide semiconductor," Jpn. J. Appl. Phys., vol. 49, no. 4S, 04DE12, April 2010.
• K. Yamanaga, S. Amakawa, K. Masu, and T. Sato, "A universal equivalent circuit model for ceramic capacitors," IEICE Trans. Electron., vol. E93-C, no. 3, pp. 347–354, March 2010.
• T. Maekawa, S. Amakawa, H. Ito, N. Ishihara, and K. Masu, "Highly energy-efficient on-chip pulsed-current-mode transmission line interconnect," in J. W. Swart, editor, Solid State Circuit Technologies, pp. 263–280, INTECH, January 2010.
• Y. Kurita, N. Motohashi, S. Matsui, K. Soejima, S. Amakawa, K. Masu, and M. Kawano, "Inter-chip wiring technology for 3-D LSI," Electrochemistry, vol. 77, no. 9, pp. 812–817, 2009.
• (Invited) K. Masu, N. Ishihara, N. Nakayama, T. Sato, and S. Amakawa, "Physical design challenges to nano-CMOS circuits," IEICE Electronics Express, vol. 6, no. 11, pp. 703–720, June 2009.
• K. Yamada, T. Sato, S. Amakawa, N. Nakayama, K. Masu, and S. Kumashiro, "Layout-aware compact model of MOSFET characteristics variations induced by STI stress," IEICE Trans. Electron., vol. E91-C, no. 7, pp. 1142–1150, July 2008.
• B. Kaestner, V. Kashcheyevs, S. Amakawa, M. B. Blumenthal, L. Li, T. J. B. M. Janssen, G. Hein, K. Pierz, T. Weimann, U. Siegner, and H. W. Schumacher, "Single-parameter nonadiabatic quantized charge pumping," Phys. Rev. B, vol. 77, 153301, April 2008.
• S. Amakawa, K. Tsukagoshi, K. Nakazato, H. Mizuta, and B. W. Alphenaar, "Single-electron logic based on multiple-tunnel junctions," in H. Nakashima, editor, Mesoscopic Tunneling Devices, 2004, pp. 71–104, Research Signpost, Kerala/India, 2004.
• H. Mizuta, Y. Furuta, T. Kamiya, Y. T. Tan, Z. A. K. Durrani, S. Amakawa, K. Nakazato, and H. Ahmed, "Nanosilicon for single-electron devices," Current Appl. Phys., vol. 4, pp. 98–101, April 2004.
• T. Altebaeumer, S. Amakawa, and H. Ahmed, "Cross-coupling in Coulomb blockade circuits: Bidirectional electron pump," J. Appl. Phys., vol. 94, no. 5, pp. 3194–3200, September 2003.
• T. Altebaeumer, S. Amakawa, and H. Ahmed, "Characteristics of two Coulomb blockade transistors separated by an island to which an oscillating potential is applied: Theory and experiment," Appl. Phys. Lett., vol. 79, no. 4, pp. 533–535, July 2001.
• H. Mizuta, H.-O. Müller, K. Tsukagoshi, D. Williams, Z. Durrani, A. Irvine, G. Evans, S. Amakawa, K. Nakazato, and H. Ahmed, "Nanoscale Coulomb blockade memory and logic devices," Nanotechnology, vol. 12, pp. 155–159, June 2001.
• S. Amakawa, H. Mizuta, and K. Nakazato, "Analysis of multiphase clocked electron pumps consisting of single-electron transistors," J. Appl. Phys., vol. 89, no. 9, pp. 5001–5008, May 2001.
• S. O'uchi, T. Tsubokura, T. Tajima, S. Amakawa, M. Fujishima, and K. Hoh, "Charging and retention times in silicon-floating-dot-single-electron memory," Jpn. J. Appl. Phys., vol. 40, no. 3B, pp. 2041–2045, March 2001.
• S. Amakawa, K. Hoh, M. Fujishima, H. Mizuta, and K. Tsukagoshi, "Scaling of the single-electron tunnelling current through ultrasmall tunnel junctions," J. Phys.: Condens. Matter, vol. 12, pp. 7223–7228, August 2000.
• S. Amakawa, K. Kanda, M. Fujishima, and K. Hoh, "A simple model of a single-electron floating dot memory for circuit simulation," Jpn. J. Appl. Phys., vol. 38, no. 1B, pp. 429–432, January 1999.
• M. Fujishima, S. Amakawa, and K. Hoh, "Circuit simulator aiming at single-electron integration," Jpn. J. Appl. Phys., vol. 37, no. 3B, pp. 1478–1482, March 1998.
• S. Amakawa, H. Majima, H. Fukui, M. Fujishima, and K. Hoh, "Single-electron circuit simulation," IEICE Trans. Electron., vol. E81-C, no. 1, pp. 21–29, January 1998.
• M. Fujishima, H. Fukui, S. Amakawa, and K. Hoh, "Proposal of a Schottky-barrier SET aiming at a future integrated device," IEICE Trans. Electron., vol. E80-C, no. 7, pp. 881–885, July 1997.
• S. Amakawa, M. Fujishima, and K. Hoh, "Correlated electron-hole transport in capacitively-coupled one-dimensional tunnel junction arrays," Jpn. J. Appl. Phys., vol. 36, no. 6B, pp. 4166–4171, June 1997.
• S. Amakawa, H. Fukui, M. Fujishima, and K. Hoh, "Estimation of cotunneling in single-electron logic and its suppression," Jpn. J. Appl. Phys., vol. 35, no. 2B, pp. 1146–1150, February 1996.

Conferences, symposia, workshops, etc.

• S. Amakawa, "Signal-flow-graph representation of weakly nonlinear networks and its applications," IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), pp. 106–108, Kagoshima, Japan, August 27, 2025.
• S. Amakawa, T. Yoshida, M. E. Gadringer, and W. Bösch, "Modal TRL de-embedding of symmetric differential transmission lines with proper reference impedance matrix transformations," 104th ARFTG Microwave Measurement Symposium, San Juan, Puerto Rico, January 21, 2025.
• S. Amakawa, S. Tanaka, M. Fujishima, and T. Yoshida, "Second-tier TRL-based characteristic impedance estimation using a longer thru," Asia-Pacific Microwave Conference, pp. 976–978, Bali, Indonesia, November 20, 2024.
• S. Amakawa, "Measurement and modeling for sub-THz CMOS design: Challenges and opportunities," Asia-Pacific Microwave Conference, pp. 864–866, Taipei, Taiwan, December 8, 2023.
• S. Amakawa, "X-parameters and metrology applications," Workshop on Advanced Techniques and Applications for Large Signal Measurements and Characterization, Asia-Pacific Microwave Conference, Taipei, Taiwan, December 5, 2023.
• S. Amakawa, "On-chip transmission lines for silicon CMOS 6G: From basics to open questions," Tutorial #5, 2023 International Conference on IC Design and Technology, Tokyo, Japan, September 25, 2023.
• S. Amakawa, "Design of silicon CMOS ICs and modules for 6G: With headaches, possible cures, and open questions in measurements," 100th ARFTG Microwave Measurement Conference, Workshop on Emerging millimeter-wave & THz measurement for 6G communication, Las Vegas, Nevada, USA, January 25, 2023.
• S. Amakawa, "Sub-THz CMOS transmission lines: Properties, characterization, and modeling," IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), p. 64, September 2, 2020.
• S. Amakawa and M. Fujishima, "300-GHz-band CMOS transmitter and receiver modules with WR-3.4 waveguide interface," IEEE MTT-S International Microwave Conference on Hardware and Systems for 5G and Beyond (IMC-5G), pp. 1–3, August 15, 2019.
• S. Amakawa and M. Fujishima, "Wideband power-line decoupling technique for millimeter-wave CMOS integrated circuits," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–4, May 29, 2019.
• S. Amakawa, "Characteristic impedance determination up to THz frequencies in light of causality," Global Symposium on Millimeter Waves (GSMM), pp. 35–37, May 23, 2019.
• S. Amakawa, A. Takeshige, S. Hara, R. Dong, S. Lee, T. Yoshida, M. Fujishima, K. Masu, and H. Ito, "Causal characteristic impedance determination using calibration comparison and propagation constant," 92nd Automatic RF Techniques Group Microwave Measurement Conference (ARFTG), pp. 1–6, January 22, 2019.
• S. Amakawa, "How does my microwave/EM simulator define complex-referenced S-parameters?," Vietnam-Japan Microwave (VJMW), pp. 112–115, June 14, 2017 (pdf).
• S. Amakawa and Y. Ito, "Graphical approach to analysis and design of gain-boosted near-f_max feedback amplifiers," European Microwave Conference (EuMC), pp. 1039–1042, October 4, 2016.
• S. Amakawa, K. Katayama, K. Takano, S. Hara, A. Kasamatsu, K. Mizuno, K. Takahashi, T. Yoshida, and M. Fujishima, "A QAM-capable 300-GHz CMOS transmitter," International Workshop on Smart Wireless Communications (SmartCom), pp. 39–46, May 17 2016.
• S. Amakawa, "Concepts and methods in on-wafer RF and microwave measurements," International Conference on Microelectronic Test Structures (ICMTS), Tutorial, March 28 2016.
• S. Amakawa, K. Katayama, K. Takano, M. Motoyoshi, T. Yoshida, and M. Fujishima, "Comparative analysis of on-chip transmission line de-embedding techniques," International Symposium on Radio-Frequency Integration Technology (RFIT), pp. 91–93, August 2015.
• S. Amakawa, R. Goda, K. Katayama, K. Takano, T. Yoshida, and M. Fujishima, "Power line decoupling up to 325 GHz in CMOS," Vietnam-Japan Microwave (VJMW), pp. 1–2, August 2015.
• S. Amakawa, R. Goda, K. Katayama, K. Takano, T. Yoshida, and M. Fujishima, "Power line decoupling up to 325 GHz in CMOS," Thailand-Japan Microwave (TJMW), pp. 1–2, August 2015.
• S. Amakawa, R. Goda, K. Katayama, K. Takano, T. Yoshida, and M. Fujishima, "Wideband CMOS decoupling power line for millimeter-wave applications," IEEE MTT-S International Microwave Symposium (IMS), pp. 1–4, May 2015.
• S. Amakawa, K. Katayama, K. Takano, T. Yoshida, and M. Fujishima, "On-wafer transmission line measurement above 100 GHz," Thailand-Japan Microwave (TJMW), pp. 1–2, November 2014.
• S. Amakawa, "Theory of gain and stability of small-signal amplifiers with lossless reciprocal feedback," Asia-Pacific Microwave Conference (APMC), pp. 1184–1186, November 2014 [Correction].
• S. Amakawa, A. Orii, K. Katayama, K. Takano, M. Motoyoshi, T. Yoshida, and M. Fujishima, "Design of well-behaved low-loss millimetre-wave CMOS transmission lines," 18th IEEE Workshop on Signal and Power Integrity (SPI), pp. 1–4, May 2014.
• S. Amakawa, A. Orii, K. Katayama, K. Takano, M. Motoyoshi, T. Yoshida, and M. Fujishima, "Process parameter calibration for millimeter-wave CMOS back-end device design with electromagnetic field analysis," International Conference on Microelectronic Test Structures (ICMTS), pp. 182–187, March 2014.
• 天川修平，折井瑛彦，丸岡元樹，片山光亮，高野恭弥，本良瑞樹，吉田毅，藤島実， 「オンチップ伝送線路評価のための試料設計」， 第33回シリコンアナログRF研究会，August 2013.
• 天川修平，「半導体、電子デバイス、配線を回路理論の立場から学び直してみる」， 第60回応用物理学会春季学術講演会， チュートリアル（ショートコース），March 2013
• 天川修平，藤島実，「多導体伝送線路系のためのS行列の定義の拡張」， 電子情報通信学会マイクロ波研究会，信学技報，vol. 112, no. 459, MW2012-165, pp. 37–38, March 2013.
• 天川修平，「物理的意味のわかりやすいTRL導出方法」， 第31回シリコンアナログRF研究会，December 2012.
• S. Amakawa, K. Takano, K. Katayama, M. Motoyoshi, T. Yoshida, and M. Fujishima, "On the choice of cascade de-embedding methods for on-wafer S-parameter measurement," International Symposium on Radio-Frequency Integration Technology (RFIT), pp. 137–139, November 2012.
• 天川修平，「Cascade de-embedding再考」， 第30回シリコンアナログRF研究会，August 2012.
• 天川修平， 「On-wafer測定に用いる散乱行列の基礎理論に関する一考察」， 第28回シリコンアナログRF研究会, March 2012.
• 天川修平， 「 Sパラ再入門」（チュートリアル講演）， 第27回シリコンアナログRF研究会，November 2011.
• S. Amakawa, K. Yamanaga, H. Ito, T. Sato, N. Ishihara, and K. Masu, "S-parameter-based modal decomposition of multiconductor transmission lines and its application to de-embedding," International Conference on Microelectronic Test Structures (ICMTS), pp. 177–180, Oxnard/California, April 2009.
• S. Amakawa, H. Ito, N. Ishihara, and K. Masu, "A simple de-embedding method for characterization of on-chip four-port networks," Advanced Metallization Conference (AMC), pp. 105–106, Del Mar/California, September 2008.
• S. Amakawa, H. Ito, and K. Masu, "Signal transmission through interconnects with repetitive loads," Advanced Metallization Conference (AMC), pp. 173–174, Albany/New York, October 2007.
• S. Amakawa, T. Uezono, T. Sato, K. Okada, and K. Masu, " Adaptable wire-length distribution with tunable occupation probability," International Workshop on System Level Interconnect Prediction (SLIP), pp. 1–8, Lakeway/Texas, March 2007 [Slides].
• S. Amakawa, K. Nakazato, and H. Mizuta, "A surface-potential-based cylindrical surrounding-gate MOSFET model," International Conference on Solid State Devices and Materials (SSDM), pp. 638–639, Tokyo/Japan, September 2003.
• S. Amakawa, K. Nakazato, and H. Mizuta, "A new approach to failure analysis and yield enhancement of very large-scale integrated systems," European Solid-State Device Research Conference (ESSDERC), pp. 147–150, September 2002.
• S. Amakawa, H. Mizuta, and K. Nakazato, "Analysis of multi-phase clocked electron pump circuits," Silicon Nanoelectronics Workshop (SNW), pp. 30–31, Kyoto/Japan, June 2001.
• S. Amakawa, H. Mizuta, and K. Nakazato, "Analysis of multi-clocked electron pump consisting of single-electron transistors," 4th International Workshop on Quantum Functional Devices, Kanazawa/Japan, 2000.
• S. Amakawa, H. Mizuta, and K. Nakazato, "Performance optimisation of single-electron pump circuits," Sixth MEL-ARI/NID Workshop, Enschede/Netherlands, 2000.
• S. Amakawa, M. Fujishima, and K. Hoh, "Single-electron tunneling through an asymmetric tunnel barrier," Sixth International Workshop on Computational Electronics (IWCE), pp. 137–140, Osaka/Japan, 1998.
• S. Amakawa, K. Kanda, M. Fujishima, and K. Hoh, "Simulation of a single-electron flash memory," International Symposium on Formation, Physics and Device Application of Quantum Dot Structures, p. 80, Sapporo/Japan, 1998.
• S. Amakawa, H. Majima, M. Fujishima, and K. Hoh, "High and low levels of simulation of single-electron circuits," International Semiconductor Device Research Symposium (ISDRS), pp. 349–352, Charlottesville/Virginia, 1997.
• S. Amakawa, M. Fujishima, and K. Hoh, "Characterization of capacitively-coupled dual tunnel junction array," International Symposium on Formation, Physics and Device Application of Quantum Dot Structures, p. 154, Sapporo/Japan, 1996.
• S. Amakawa, H. Fukui, M. Fujishima, and K. Hoh, "Cotunneling-tolerant single-electron logic," International Conference on Solid State Devices and Materials (SSDM), pp. 207–209, Osaka/Japan, 1995.

Others

• K. Ohmori and S. Amakawa, "Variable-temperature broadband noise characterization of MOSFETs for cryogenic electronics: From room temperature down to 3 K," EDTM, March 2023 (pdf).
• 天川修平，「Sパラメータと伝送線路の考え方」，電子情報通信学会Webinarチュートリアルシリーズ，June 16, 2022.
• 天川修平， 「ミリ波オンウェハー測定：暗部と光明」， Microwave Workshops & Exhibition (MWE)， ワークショップ FR1B，November 26, 2021.
• A. Pärssinen ed., "White Paper on RF enabling 6G –– opportunities and challenges from technology to spectrum," 6G Research Visions, no. 13, 6G Flagship, University of Oulu, April 2021.
• 天川修平， 「Sパラメータ利用の落とし穴（３）：穴の中で、シミュレーションと測定の深掘りをしてみる」， Microwave Workshops & Exhibition (MWE)， 入門講座 TH6A，November 30, 2017.
• 天川修平， 「Sパラメータ特論[III・完]––基準インピーダンスの設定––」 (pdf)， 電子情報通信学会誌，vol. 100, no. 7, pp. 655–661, July 2017.
• 天川修平， 「Sパラメータ特論[II]––Sパラメータの諸性質––」 (pdf)， 電子情報通信学会誌，vol. 100, no. 6, pp. 511–516, June 2017.
• 天川修平， 「Sパラメータ特論[I]––反射係数の二つの定義––」 (pdf)， 電子情報通信学会誌，vol. 100, no. 5, pp. 381–386, May 2017.
• 天川修平， 「続Sパラメータ利用の落とし穴：VNAキャリブレーションとは何か（穴にはまった人からの報告）」， Microwave Workshops & Exhibition (MWE)， 入門講座 FR6A，December 2, 2016.
• 天川修平， 「Sパラメータ利用の落とし穴」， Microwave Workshops & Exhibition (MWE)， 入門講座 FR6A，November 27, 2015.
• 藤島実，天川修平， 「電気計測（高周波測定）のコツ」， 応用物理，vol. 84, no. 5, pp. 453–457, May 2015.
• 石原昇，天川修平，益一哉， 「CMOS 集積回路とMEMSの融合」， 電子情報通信学会誌，vol. 93, no. 11, pp. 928–932, November 2010.
• 天川修平，岡田健一，石原昇，益一哉，上道雄介，畠山英樹，相沢卓也，「 シリコン基板上の低損失ミリ波帯受動素子」，フジクラ技報， vol. 1, no. 120, pp. 49–52, April 2011.

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